Susie E. Maestre

Assistant Professor

Susie Maestre is a faculty member of the Electrical and Electronics Engineering department.

BS Electronics and Communications Engineering, Mindanao State University - Marawi (Cum Laude, March 2014)
- Registered Electronics Engineer, 2014
MS Electrical Engineering (Microelectronics), Mindanao State University - IIT (2022)

S. A. Khalid, S. E. Maestre and K. M. Madrid-Khalid, "Open-LUT: Interactive gm/ID Lookup Tables for MOSFET Sizing in Open-Source PDKs," 2025 10th International Conference on Integrated Circuits and Microsystems (ICICM), Hefei, China, 2025, pp. 344-353, doi: 10.1109/ICICM66614.2025.11316023
K. M. Cañonero, J. S. Bernales, A. G. Macapundag, S. A. Khalid and S. E. Maestre, "Design of a Bandgap Voltage Reference for an 8-bit SAR-ADC for Powerline Monitoring using SKY130 PDK," 2025 10th International Conference on Integrated Circuits and Microsystems (ICICM), Hefei, China, 2025, pp. 427-432, doi: 10.1109/ICICM66614.2025.11315948
S. Maestre, A. Gumera, J. Hora and M. J. de Guzman, "Improving Digital Design PPA (Performance, Power, Area) using iSpatial Physical Restructuring," 2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Phuket, Thailand, 2022, pp. 647-651

PCIEERD-DOST Research Project; 2026-2027

"CHIP IP BLOCKS Proj-3: Development of Design Analysis and Methodologies for High Linearity and Fast Response Time Track-and-Hold (T/H) Circuit in 5G-Advanced and 6G Applications"

Role: Project Leader